1. Overview of SAR ADC

A SAR (Successive Approximation Register) ADC converts an analog voltage into a digital output using a binary search algorithm. It consists of:

• Sample-and-Hold (S/H): Captures input voltage.
• Comparator: Compares input with DAC output.
• DAC: Converts SAR register value back to analog.
• SAR Register: Implements binary search for N bits.
• Control Logic: Coordinates clock and bit scanning.

2. Conversion Algorithm

For an 8-bit SAR ADC:

1. Sample input voltage and hold.
2. Set MSB to 1, all others 0.
3. DAC converts SAR code → analog.
4. Comparator decides if bit stays 1 or cleared.
5. Repeat for next lower bit until LSB.
6. Final SAR register contains digital output.

3. Detailed Logic Diagram

SAR ADC (Registre à Approximations Successives) 结构图

Plus d’infos : Convertisseur analogique-numérique (Wikipédia français)

图像使用许可：CC BY‑SA 2.5。SAR 是 “Successive Approximation Register”（逐次逼近寄存器）。

Block diagram of SAR ADC showing Sample-and-Hold, Comparator, DAC, SAR Register, and Control Logic.

4. SAR Register Internal Logic

SAR register uses N flip-flops and a control FSM to implement the binary search:

for i = N-1 downto 0:
    set SAR[i] = 1
    V_DAC = DAC(SAR)
    if V_DAC > V_in:
        SAR[i] = 0

5. Features & Advantages

• Medium-high resolution: 8–18 bits
• Moderate to fast conversion time
• Low power consumption compared to Flash ADC
• On-chip voltage reference possible